In recent years, as semiconductor integrated circuit apparatuses have become highly integrated, highly functional and highly speedy, the devices have been miniaturized more and more. Along with this, not only the horizontal miniaturization as seen in the miniaturization of the gate length of transistors, but the vertical miniaturization as seen in the realization of a very thin gate insulation layer has progressed as well. On the other hand, since such a miniaturization of devices increases the electrostatic capacitance (parasitic capacitance) between wires, and between a silicon substrate and wires, it causes a problem that reduction in power consumption of devices or speed-up of devices cannot be achieved effectively.
Although an insulating layer with a low electric permittivity is under development for the purpose of reducing the parasitic capacitance between wires, what is attracting attention recently as effective means for achieving the purpose is an SOI (Silicon-On-Insulator) wafer which is formed by forming an oxide layer (insulation layer) called BOX (Buried OXide) on a surface of a silicon wafer as a supporting substrate, and forming, on the BOX, a relatively thin, monocrystalline silicon layer. In recent years, an application of the SOI wafer to a three-dimensional integrated circuit is under study, as can be seen in an SOI wafer in which semiconductor devices have been further stacked for higher integration.